So the code instructs the FPGA (or, more accurately, the Verilog compiler) to examine the number and set dispoutput based on the input. The <= character, by the way, are a non-blocking assignment.

Hence, it relieves the system’s CPU from the task of polling in a multi-level priority system. This paper deals with implementation of a priority interrupt controller using Verilog language.

We also like that the tutorial used some of the more interesting features of Vivado like automatic verification. Even if you are experienced with Verilog, there are some good tips here.