Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
EDN

Simplify FPGA Design and Test Projects

During the 2012 Design West conference and exhibition I talked with Frederic Leens, founder of Byte Paradigm, about a new approach to “instrument” and test designs within an FPGA. Byte Paradigm ...
EDN

Internal test in FPGA design

http://www.xilinx.comAs the density of field-programmable-gate arrays (FPGAs) continues to increase, engineers are challenged to come up with ways to test and verify ...
New Electronics

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Microsemi has announced a collaboration with MathWorks to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development ...
Design-Reuse

Automatic C-to-VHDL testbench generation shortens FPGA development time

Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad ...
Semiconductor Engineering

Using FPGAs For Emulation

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big ...