Semiconductor Engineering

How UVM Callbacks Simplify Assertion Validation

Assertions bring immediate benefits to the whole design and verification cycle; thus any challenges engineers face in coding and testing them are worth resolving. When a large number of assertions are ...
Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
Electronic Design

Validate Assertions in Packet-Based Protocol Designs Using UVM Callbacks

Assertions bring immediate benefits to the entire design and verification cycle. To use assertions effectively in the verification cycle, they need to be exercised for checking legal design behavior ...